An Ultra-Compact High-Power CMOS Power Amplifier for Millimeter-Wave 5G Communications

Project Description

The millimeter-wave spectrum offers many opportunities for high-speed wireless communications. For instance, the abundance of available bandwidth in the FR2 band (24 – 72 GHz) enables multi-gigabit/s data rates for unprecedented wireless connectivity. However, the increase in frequency results in higher path loss, requiring the use of phased arrays transmitters to provide high output power for adequate communication distance and fidelity.

The power amplifier is a key circuit block in a transmitter chain, providing the necessary output power at the antenna for long-range communications. However, in CMOS technologies, power amplifiers suffer from low output power compared to III-V technologies (i.e. GaN) due to low device breakdown voltages. Therefore, on-chip power combiners are needed to obtain adequate output power. Conventional on-chip power combiners typically have large area, making it difficult to physically integrate into an array.

This project explores a highly compact method of on-chip power combining in conjunction with a stacked transistor topology to provide extremely high-power density in a GlobalFoundries 45nm RFE CMOS process. The power amplifier, driver, and matching networks will be designed and simulated. Layout of critical components will be done.

In this project, the student will:

1. Learn CMOS power amplifier design fundamentals and tradeoffs
2. Design and simulate a stacked power amplifier core
3. Design and simulate matching networks
4. Layout of critical circuit components
5. Tapeout if time permits

Requirements

• Analog Integrated Circuits
• Communication Circuits
• Electromagnetic Simulation Experience (Desired, not required)

Project components

• 10% Familiarization of 45nm RFE process
• 30% Schematic Design & Simulation
• 40% Electromagnetic Simulation
• 20% Layout

Contact

Edward Liu : edwliu [at] iis.ee.ethz.ch

Prof. Dr. Hua Wang : hua.wang [at] iis.ee.ethz.ch